1. Field of the Invention
The present invention generally relates to Dynamic Random Access Memories (DRAMs) and, more particularly to DRAMs with Built In Self Test (BIST) Capability.
2. Background Description
State of the art Dynamic Random Access Memories (DRAM) and logic chips, such as microprocessors, may include Built In Self Test (BIST) capability. The BIST logic tests the DRAM or logic according to predefined tests to uncover any defective array elements.
Such a state of the art logic and DRAM is designed to function at what are defined to be worst case conditions. Normally, such a conservative worst case design includes some design margin to assure functionality that limits the microprocessor's or DRAM's actual performance to something less than the its full capability. Design margin verses performance is a trade off that designers must make at design to maximize chip manufacturing yield and guarantee chip functionality to specification.
Consequently, even though such a chip may include individual circuits capable of higher performance, its performance restricted by its slowest circuits. Further, even though some circuits might be selectively tuned in place, for an overall chip performance improvement, all circuits are set for the slowest circuits.
Thus, there is a need for integrated circuit chips wherein individual circuits may be tuned for optimum performance.